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? semiconductor components industries, llc, 2007 october, 2007 - rev. 25 1 publication order number: ncv8508/d ncv8508 5.0 v, 250 ma ldo with watchdog and reset the ncv8508 is a precision micropower low dropout (ldo) voltage regulator. the part contains many of the required features for powering microprocessors. its robustness makes it suitable for severe automotive environments. in addition, the ncv8508 is ideal for use in battery operated, microprocessor controlled equipment because of its extremely low quiescent current. features ? output voltage: 5.0 v ? 3.0% output voltage ? i out up to 250 ma ? quiescent current independent of load ? micropower compatible control functions: ? wakeup ? watchdog ? reset ? low quiescent current (100 a typ) ? protection features: ? thermal shutdown ? short circuit ? 45 v operation ? internally fused leads in so-16l package ? ncv prefix for automotive and other applications requiring site and change control ? aec qualified ? ppap capable ? pb-free package is available* figure 1. application circuit c1* v out gnd v in wdi ncv8508 1.0 f i/o i/o reset reset 0.1 f c2 microprocessor delay r delay 60 k v bat *c1 required if regulator is located far from power supply filter. v dd wakeup mra4004t3 *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. so-16l dw suffix case 751g 1 16 see detailed ordering and shipping information in the package dimensions section on page 23 of this data sheet. ordering information marking diagrams 1 ncv85085 awlyywwg 16 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb-free package http://onsemi.com d 2 pak-7 dps suffix case 936ab ncv85085 awlywwg 1 v8508 alyw 1 8 so-8 ep pd suffix case 751ac 1 8
ncv8508 http://onsemi.com 2 v in v out 1 16 nc sense wdi nc gnd gnd gnd gnd wakeup nc reset nc delay nc pin connections 1 so-16l d 2 pak-7 tab = gnd lead 1. v out 2. v in 3. wdi 4. gnd 5. wakeup 6. reset 7. delay v out sense gnd delay v in wdi wakeup reset 1 8 so-8 ep package pin description package pin # pin symbol function d 2 pak-7 so-16l so-8 ep 1 8 4 v out regulated output voltage 3.0%. 2 9 5 v in supply voltage to the ic. 3 11 6 wdi cmos compatible input lead. the watchdog function monitors the falling edge of the incoming signal. 4 4, 5, 12, 13 2 gnd ground connection. 5 14 7 wakeup cmos compatible output consisting of a continuously generated signal used to wake up the microprocessor from sleep mode. 6 15 8 reset cmos compatible output lead reset goes low whenever v out drops by more than 7.0% from nominal, or during the absence of a correct watchdog signal. 7 16 1 delay buffered bandgap voltage used to create timing current for reset and wakeup from r delay. - 1-3, 6, 10 - nc no connection. - 7 3 sense kelvin connection which allows remote sensing of the output voltage for improved regulation. connect to v out if remote sensing is not required.
ncv8508 http://onsemi.com 3 - + + - wakeup circuit timing circuit falling edge detect watchdog circuit thermal shutdown current limit charge pump bandgap reference v in reset v out wakeup wdi delay figure 2. block diagram - + 1.25 v 11 v internally connected on 7 lead d 2 pak sense maximum ratings rating value unit input voltage, v in (dc) -0.3 to 45 v peak transient voltage (46 v load dump @ v in = 14 v) 60 v output voltage, v out -0.3 to 18 v esd susceptibility: human body model machine model 2.0 150 kv v logic inputs/outputs (reset , wdi, wakeup) -0.3 to +7.0 v operating junction temperature, t j -40 to150 c storage temperature range, t s -55 to +150 c peak reflow soldering temperature: reflow: (note 1) 240 peak 260 peak (pb-free) (note 3) c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. 60 second maximum above 183 c. 2. depending on thermal properties of substrate r ja = r jc + r jca . 3. -5 c/+0 c allowable conditions, applies to both pb and pb-free devices. thermal characteristics see package thermal data section (page 10)
ncv8508 http://onsemi.com 4 electrical characteristics (-40 c t j 125 c; 6.0 v v in 28 v, 100 a i out 150 ma, c 2 = 1.0 f, r delay = 60 k; unless otherwise specified.) characteristic test conditions min typ max unit output output voltage - 4.85 5.00 5.15 v dropout voltage (v in - v out ) i out = 150 ma. note 4 - 450 900 mv load regulation v in = 14 v, 100 a i out 150 ma - 5.0 30 mv line regulation 6.0 v v in 28 v, i out = 5.0 ma - 5.0 50 mv current limit - 250 400 - ma thermal shutdown guaranteed by design 150 180 210 c quiescent current v in = 12 v, i out = 150 ma, (see figure 6) - 100 150 a reset threshold - 4.50 4.65 4.80 v output low r load = 10 k to v out , v out 1.0 v r load = 5.1 k to v out , v out 1.0 v - 0.2 0.4 0.4 0.8 v output high r load = 10 k to gnd r load = 5.1 k to gnd v out - 0.5 v out - 1.0 v out - 0.25 v out - 0.5 - v delay time v in = 14 v, r delay = 60 k, i out = 5.0 ma v in = 14 v, r delay = 120 k, i out = 5.0 ma 2.0 - 3.0 6.0 4.0 - ms ms watchdog input threshold high - 70 - - %v out threshold low - - - 30 %v out hysteresis - - 100 - mv input current wdi = 6.0 v - 0.1 +10 a pulse width 50% wdi falling edge to 50% wdi rising edge and 50% wdi rising edge to 50% wdi falling edge, (see figure 5) 5.0 - - s wakeup output (v in = 14 v, i out = 5.0 ma) wakeup period see figures 4 and 5, r delay = 60 k see figures 4 and 5, r delay = 120 k 18 - 25 50 32 - ms ms wakeup duty cycle nominal see figure 3 45 50 55 % reset high to wakeup rising delay time r delay = 60 k 50% reset rising edge to 50% wakeup edge, r delay = 120 k (see figures 3 and 4) 9.0 - 12.5 25 16 - ms ms wakeup response to watchdog input 50% wdi falling edge to 50% wakeup falling edge - 0.1 5.0 s wakeup response to reset 50% reset falling edge to 50% wakeup falling edge. v out = 5.0 v 4.5 v - 0.1 5.0 s output low r load = 10 k to v out , v out 1.0 v r load = 5.1 k to v out , v out 1.0 v - 0.2 0.4 0.4 0.8 v output high r load = 10 k to gnd r load = 5.1 k to gnd v out - 0.5 v out - 1.0 v out - 0.25 v out - 0.5 - v delay output voltage i delay = 50 a. note 5 - 1.25 - v 4. measured when the output voltage has dropped 100 mv from the nominal value. (see figure 12) 5. current drain on the delay pin directly affects the delay time, wakeup period, and the reset to wakeup delay time.
ncv8508 http://onsemi.com 5 timing diagrams watchdog pulse width v in reset wakeup wdi v out wakeup duty cycle = 50% power up microprocessor sleep mode normal operation with varying watchdog signal reset high to wakeup delay time por figure 3. power up, sleep mode and normal operation figure 4. error condition: watchdog remains low and a reset is issued v in reset wakeup wdi v out por reset high to wakeup delay time reset delay time reset high to wakeup delay time wakeup period por reset wakeup wdi v out watchdog pulse width reset threshold por power down wakeup period figure 5. power down and restart sequence wdi pulse must occur with wakeup in low state for 50% duty cycle. reference figure 17 for occurrence of wdi with wakeup in high state.
ncv8508 http://onsemi.com 6 typical performance characteristics figure 6. quiescent current vs output current 0 90 i out , ma 50 100 150 200 250 120 110 100 i q , a -40 c +25 c +125 c 0 0 switching current, ma 50 100 150 200 250 -700 v out transient, mv -400 -300 -200 -100 100 f esr = 1.3 figure 7. load transient response -40 2.7 temperature, c -20 0 140 3.7 por delay, ms 3.6 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 20 40 60 80 100 120 figure 8. por delay vs temp, r delay = 60 k figure 9. por delay vs r delay 15 0 r delay , k 60 240 14 por delay, ms 12 10 8 6 4 2 105 150 195 -40 23.0 temperature ( c) 20 40 60 80 100 120 140 27.0 26.5 wakeup period, ms 26.0 25.5 25.0 24.5 24.0 23.5 -20 0 figure 10. wakeup period vs temp, r delay = 60 k figure 11. wakeup period vs r delay 15 0 r delay , k 60 240 100 r delay , ms 90 80 70 60 50 40 30 20 10 105 150 195 -500 -600 10 f esr = 3.4 1.0 f esr = 4.6
ncv8508 http://onsemi.com 7 typical performance characteristics figure 12. dropout voltage vs output current figure 13. output voltage vs temperature figure 14. output current vs input voltage 0 dropout voltage (v) 0.0 output current (ma) 0.1 0.2 0.3 0.4 0.5 0.6 1.0 25 50 75 100 150 125 +25 c +125 c -40 c -40 output voltage (v) 4.90 temperature ( c) 4.95 5.00 5.05 5.10 -25 125 -10 5 203550658095110 1.0 i out ( m a) 0 v in (v) 40 60 80 100 120 140 160 1.5 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v in = 14 v i out = 5.0 ma r l = 33 1000 100 10 1 0 5 10 15 20 25 30 35 40 45 esr ( ) output current (ma) figure 15. output capacitor esr unstable region stable region c = 1.0 f, 10 f 175 200 250 225 0.7 0.8 0.9 definition of terms dropout voltage: the input-output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. measured when the output voltage has dropped 100 mv from the nominal value obtained at 14 v input, dropout voltage is dependent upon load current and junction temperature. input voltage: the dc voltage applied to the input terminals with respect to ground. line regulation: the change in output voltage for a change in the input voltage. the measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. load regulation: the change in output voltage for a change in load current at constant chip temperature. quiescent curr ent: the part of the positive input current that does not contribute to the positive load current. the regulator ground lead current. ripple rejection: the ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage. current limit: peak current that can be delivered to the output.
ncv8508 http://onsemi.com 8 detailed operating description the ncv8508 is a precision micropower voltage regulator with very low quiescent current (100 a typical at 250 ma load). a typical dropout voltage is 450 mv at 150 ma. microprocessor control logic includes watchdog, wakeup and reset . this unique combination of extremely low quiescent current and full microprocessor control makes the ncv8508 ideal for use in battery operated, microprocessor controlled equipment in addition to being a good fit in the automotive environment. the ncv8508 wakeup function brings the microprocessor out of sleep mode. the microprocessor in turn signals its wakeup status back to the ncv8508 by issuing a watchdog signal. the watchdog logic function monitors an input signal (wdi) from the microprocessor. the ncv8508 responds to the falling edge of the watchdog signal which it expects at least once during each wakeup period. when the correct watchdog signal is received, a falling edge is issued on the wakeup signal line. reset is independent of v in and operates correctly to an output voltage as low as 1.0 v. a signal is issued in any of three situations. during power up, the reset is held low until the output vo ltage is in regulation. during operation, if the output voltage shifts below the regulation limits, the reset toggles low and remains low until proper output voltage regulation is restored. finally, a reset signal is issued if the regulator does not receive a watchdog signal within the wakeup period. the reset pulse width, wakeup signal frequency, and wakeup delay time are all set by one external resistor, r delay . the delay pin is a buffered bandgap voltage (1.25 v). it can be used as a reference for an external tracking regulator as shown in figure 16. the regulator is protected against short circuit and thermal runaway conditions. the device runs through 45 volt transients, making it suitable for use in automotive environments. v out gnd v in ncv8508 1.0 f 0.1 f delay v bat v in figure 16. application circuit cs8182 10 f 0.1 f 60 k gnd adj mra4004t3 v ref /enable 3.9 k 12 k 200 ma 5 v
ncv8508 http://onsemi.com 9 circuit description functional description to reduce the drain on the battery, a system can go into a low current consumption mode whenever it is not performing a main routine. the w akeup signal is generated continuously and is used to interrupt a microcontroller that is in sleep mode. the nominal output is a 5.0 volt square wave (voltage generated from v out ) with a duty cycle of 50% at a frequency that is determined by a timing resistor, r delay . when the microprocessor receives a rising edge from the wakeup output, it must issue a w atchdog pulse and check its inputs to decide if it should resume normal operations or remain in the sleep mode. the first falling edge of the watchdog signal causes the wakeup to go low within 2.0 s (typ) and remain low until the next wakeup cycle (see figure 17). other watchdog pulses received within the same cycle are ignored (figure 3). during power up, reset is held low until the output voltage is in regulation. during operation, if the output voltage shifts below the regulation limits, the reset toggles low and remains low until proper output voltage regulation is restored. after the reset delay, reset returns high. the watchdog circuitry continuously monitors the input watchdog signal (wdi) from the microprocessor. the absence of a falling edge on the w atchdog input during one wakeup cycle will cause a reset pulse to occur at the end of the wakeup cycle. (see figure 4). the wakeup output is pulled low during a reset regardless of the cause of the reset . after the reset returns high, the wakeup cycle begins again (see figure 4). the reset delay time, wakeup signal frequency and reset high to w akeup delay time are all set by one external resistor r delay . wakeup period = (4.17 10 -7 )r delay reset delay time = (5.21 10 -8 )r delay reset high to wakeup delay time = (2.08 10 -7 )r delay resistor temperature coefficient and tolerance as well as the tolerance of the ncv8508 must be taken into account in order to get the correct system tolerance for each parameter. figure 17. wakeup response to wdi wakeup wdi wakeup response to wdi figure 18. wakeup response to reset (low voltage) wakeup response to reset reset wakeup
ncv8508 http://onsemi.com 10 thermal data recommend thermal data for soic-16 package parameter test conditions typical value units min-pad board (note 6) 1?-pad board (note 7) junction-to-lead (psi-jl , jl ) 20 15 c/w junction-to-ambient (r ja , ja ) 100 83 c/w 6. 1 oz. copper, 94 mm 2 copper area, 0.062 thick fr4. 7. 1 oz. copper, 767 mm 2 copper area, 0.062 thick fr4. figure 19. min pad pcb layout figure 20. min pad pcb layout figure 21. internal construction of the package (notice pins 4, 5 and 12, 13 are connected to flag)
ncv8508 http://onsemi.com 11 table 1. soic 16-lead thermal rc network models 96 mm 2 767 mm 2 96 mm 2 767 mm 2 cu area cauer network foster network c's c's units tau tau units 1 1.84e-06 1.84e-06 w-s/c 2.99e-07 2.99e-07 sec 2 8.69e-06 8.69e-06 w-s/c 4.40e-06 4.40e-06 sec 3 2.61e-05 2.61e-05 w-s/c 4.62e-05 4.62e-05 sec 4 8.98e-05 8.98e-05 w-s/c 5.08e-04 5.08e-04 sec 5 2.30e-03 2.30e-03 w-s/c 8.93e-03 8.95e-03 sec 6 2.99e-02 3.07e-02 w-s/c 2.04e-01 2.19e-01 sec 7 1.79e-01 1.90e-01 w-s/c 3.26e+00 2.75e+00 sec 8 7.79e-01 9.94e-01 w-s/c 3.21e+01 2.19e+01 sec 9 5.34e+00 3.98e+00 w-s/c 1.24e+02 1.20e+02 sec r's r's r's r's 1 0.199 0.199 c/w 0.123 0.123 c/w 2 0.598 0.598 c/w 0.349 0.349 c/w 3 1.795 1.795 c/w 1.057 1.057 c/w 4 4.085 4.085 c/w 4.61 4.61 c/w 5 3.977 3.977 c/w 3.87 3.89 c/w 6 7.509 7.833 c/w 5.77 5.99 c/w 7 19.886 15.247 c/w 13.17 11.38 c/w 8 40.307 24.781 c/w 28.85 15.52 c/w 9 18.193 21.446 c/w 38.75 37.05 c/w note: bold face items in the cauer network above, represent the package without the external thermal system. the bold face item s in the foster network are computed by the square root of time constant r(t) = 225 * sqrt(time(sec)). the constant is derived base d on the active area of the device with silicon and epoxy at the interface of the heat generation. the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by time constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i 1-e -t tau i
ncv8508 http://onsemi.com 12 ja vs copper spreader area 70 75 80 85 90 95 100 0 100 200 300 400 500 600 700 800 figure 22. soic 16-lead ja as a function of the pad copper area including traces, board material 1 oz 2 oz ja ( c/w) copper area (mm 2 ) figure 23. 16 lead sow (4 leads fused), ja as a function of the pad copper area (2 oz. cu thickness), board material = 0.0625 g-10/r-4 40 70 90 100 thermal resistance, junction-ambient, r ja , ( c/w) 0 copper area (inch 2 ) 0.5 1.0 1.5 2.0 3.0 80 60 50 2.5 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (sec) figure 24. soic 16-lead single pulse heating curve cu area 94 mm 2 cu area 767 mm 2 r(t) ( c/w) 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (sec) figure 25. soic 16-lead thermal duty cycle curves on 1? spreader test board r(t) ( c/w) single 50% duty cycle 20% 10% 5% 1% cu area 767 mm 2 , 1 oz cu
ncv8508 http://onsemi.com 13 junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n time constants are not simple rc products. amplitudes of mathematical solution are not the resistance values. ambient (thermal ground) figure 26. grounded capacitor thermal network (?cauer? ladder) junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n each rung is exactly characterized by its rc-product time constant; amplitudes are the resistances. ambient (thermal ground) figure 27. non-grounded capacitor thermal ladder (?foster? ladder)
ncv8508 http://onsemi.com 14 recommend thermal data for d 2 pak-7 package parameter test conditions typical value units min-pad board (note 8) 1?-pad board (note 9) junction-to-lead (psi-jl , jl ) 6.0 6.0 c/w junction-to-ambient (r ja , ja ) 78 44 c/w 8. 1 oz. copper, 118 mm 2 copper area, 0.062 thick fr4. 9. 1 oz. copper, 626 mm 2 copper area, 0.062 thick fr4. package construction without mold compound various copper areas used for heat spreading active area (red) times 2 (only showing 1/2 symmetry) figure 28. pcb layout and package construction for simulation
ncv8508 http://onsemi.com 15 table 2. d 2 pak 7-lead thermal rc network models 118 mm 2 626 mm 2 118 mm 2 626 mm 2 cu area cauer network foster network c's c's units tau tau units 1 1.45e-06 1.45e-06 w-s/c 1.00e-07 1.00e-07 sec 2 5.55e-06 5.58e-06 w-s/c 1.00e-06 1.00e-06 sec 3 1.57e-05 1.59e-05 w-s/c 1.00e-05 1.00e-05 sec 4 5.11e-05 5.22e-05 w-s/c 0.000 0.000 sec 5 3.48e-04 5.94e-04 w-s/c 0.001 0.002 sec 6 1.07e-02 6.62e-02 w-s/c 0.006 0.029 sec 7 2.65e-02 1.55e-01 w-s/c 0.020 0.080 sec 8 0.524 0.413 w-s/c 1.43 2.63 sec 9 0.490 2.441 w-s/c 6.52 3.6 sec 10 0.843 0.410 w-s/c 104.512 95.974 sec r's r's r's r's 1 0.089 0.089 c/w 5.25e-02 5.25e-02 c/w 2 0.210 0.208 c/w 1.14e-01 1.14e-01 c/w 3 0.637 0.624 c/w 3.59e-01 3.59e-01 c/w 4 1.899 2.107 c/w 1.5 1.9 c/w 5 1.883 2.454 c/w 2.6 3.0 c/w 6 1.398 0.952 c/w 0.1 0.1 c/w 7 0.315 0.360 c/w 1.7 0.9 c/w 8 14.348 7.042 c/w 0.1 0.1 c/w 9 5.621 20.823 c/w 7.2 4.6 c/w 10 51.986 9.649 c/w 64.8 33.3 c/w note: bold face items in the cauer network above, represent the package without the external thermal system. the bold face item s in the foster network are computed by the square root of time constant r(t) = 166 * sqrt(time(sec)). the constant is derived base d on the active area of the device with silicon and epoxy at the interface of the heat generation. the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by time constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i 1-e -t tau i
ncv8508 http://onsemi.com 16 ja vs copper spreader area 0 20 40 60 80 100 120 0 100 200 300 400 500 600 700 800 ja ( c/w) copper area (mm 2 ) figure 29. d 2 pak 7-lead ja as a function of the pad copper area including traces, board material 1 oz 2 oz 0.01 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (sec) cu area 118 mm 2 cu area 626 mm 2 r(t) ( c/w) figure 30. d 2 pak 7-lead single pulse heating curve 0.01 0.1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse duration (sec) 1 r(t) ( c/w) single 50% duty cycle 20% 10% 5% 1% cu area 626 mm 2 , 1 oz cu figure 31. d 2 pak 7-lead thermal duty cycle curves on 1? spreader test board
ncv8508 http://onsemi.com 17 junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n time constants are not simple rc products. amplitudes of mathematical solution are not the resistance values. ambient (thermal ground) figure 32. grounded capacitor thermal network (?cauer? ladder) junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n each rung is exactly characterized by its rc-product time constant; amplitudes are the resistances. ambient (thermal ground) figure 33. non-grounded capacitor thermal ladder (?foster? ladder)
ncv8508 http://onsemi.com 18 recommend thermal data for soic-8 ep package parameter test conditions typical value units pad is soldered to pcb copper min-pad board (note 10) 1?-pad board (note 11) junction-to-lead (psi-jl , jl ) 64 54 c/w junction-to-lead (psi-jpad, jp ) 14 11 c/w junction-to-ambient (r ja , ja ) 122 84 c/w 10. 1 oz. copper, 54 mm 2 copper area, 0.062 thick fr4. 11. 1 oz. copper, 717 mm 2 copper area, 0.062 thick fr4. 8-soic ep half symmetry copper pad layout 25 x 25mm bottom view with mold compound top view without and without mold compound figure 34. internal construction of the package and pcb layout for multiple pad area
ncv8508 http://onsemi.com 19 table 3. soic 8-lead ep thermal rc network models 54 mm 2 717 mm 2 54 mm 2 717 mm 2 cu area cauer network foster network c's c's units tau tau units 1 2.28e-06 2.28e-06 w-s/c 2.99e-07 2.99e-07 sec 2 1.08e-05 1.08e-05 w-s/c 4.40e-06 4.40e-06 sec 3 3.24e-05 3.24e-05 w-s/c 4.36e-05 4.36e-05 sec 4 9.71e-05 9.71e-05 w-s/c 3.59e-04 3.74e-04 sec 5 6.28e-04 7.55e-04 w-s/c 3.17e-03 4.59e-03 sec 6 7.13e-03 1.49e-02 w-s/c 0.030 0.162 sec 7 1.54e-02 9.28e-02 w-s/c 0.341 0.473 sec 8 6.16e-02 1.72e-01 w-s/c 2.909 1.653 sec 9 1.94e-01 3.83e-01 w-s/c 16.126 8.488 sec 10 1.52e+00 2.41e+00 w-s/c 54.334 71.562 sec r's r's r's r's 1 0.161 0.161 c/w 0.11 0.11 c/w 2 0.482 0.482 c/w 0.26 0.26 c/w 3 1.445 1.445 c/w 0.73 0.73 c/w 4 3.00 3.00 c/w 2.60 2.83 c/w 5 4.47 5.34 c/w 4.80 5.82 c/w 6 5.92 12.21 c/w 2.98 8.95 c/w 7 20.11 16.03 c/w 12.20 0.61 c/w 8 51.85 4.89 c/w 26.10 12.91 c/w 9 68.87 15.34 c/w 62.22 16.96 c/w 10 27.52 22.36 c/w 71.83 32.09 c/w note: bold face items in the cauer network above, represent the package without the external thermal system. the bold face item s in the foster network are computed by the square root of time constant r(t) = 225 * sqrt(time(sec)). the constant is derived base d on the active area of the device with silicon and epoxy at the interface of the heat generation. the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by time constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i 1-e -t tau i
ncv8508 http://onsemi.com 20 ja vs copper spreader area 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 0 50 100150200250300350400450500550600650700750800 ja ( c/w) copper area (mm 2 ) figure 35. soic 8-lead ep ja as a function of the pad copper area including traces, board material 1 oz 2 oz 0.1 1 10 100 1000 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (sec) cu area 54 mm 2 cu area 717 mm 2 r(t) ( c/w) figure 36. soic 8-lead ep single pulse heating curve 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (sec) r(t) ( c/w) single 50% duty cycle 20% 10% 5% 1% cu area 767 mm 2 , 1 oz cu figure 37. soic 8-lead thermal duty cycle curves on 1? spreader test board
ncv8508 http://onsemi.com 21 junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n time constants are not simple rc products. amplitudes of mathematical solution are not the resistance values. ambient (thermal ground) figure 38. grounded capacitor thermal network (?cauer? ladder) junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n each rung is exactly characterized by its rc-product time constant; amplitudes are the resistances. ambient (thermal ground) figure 39. non-grounded capacitor thermal ladder (?foster? ladder)
ncv8508 http://onsemi.com 22 application notes calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 40) is: p d(max) [v in(max) v out(min) ]i out(max) (1) v in(max) i q where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . smart regulator ? i q control features i out i in figure 40. single output regulator with key performance parameters labeled v in v out } once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each m aterial in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3) where: r jc = the junction-to-case thermal resistance, r cs = the case-to-heatsink thermal resistance, and r sa = the heatsink-to-ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in data sheets of heatsink manufacturers.
ncv8508 http://onsemi.com 23 ordering information device output voltage package shipping ? ncv8508dw50 5.0 v so-16l 47 units / rail ncv8508dw50g 5.0 v so-16l (pb-free) 47 units / rail ncv8508dw50r2 5.0 v so-16l 1000 / tape & reel ncv8508dw50r2g 5.0 v so-16l (pb-free) 1000 / tape & reel ncv8508d2t50 5.0 v d 2 pak-7 50 units / rail ncv8508d2t50g 5.0 v d 2 pak-7 (pb-free) 50 units / rail ncv8508d2t50r4 5.0 v d 2 pak-7 750 / tape & reel ncv8508d2t50r4g 5.0 v d 2 pak-7 (pb-free) 750 / tape & reel NCV8508PD50 5.0 v so-8 ep 98 units / rail NCV8508PD50g 5.0 v so-8 ep (pb-free) 98 units / rail NCV8508PD50r2 5.0 v so-8 ep 2500 / tape & reel NCV8508PD50r2g 5.0 v so-8 ep (pb-free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv8508 http://onsemi.com 24 package dimensions d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 q 0 7 so-16l dw suffix case 751g-03 issue c
ncv8508 http://onsemi.com 25 package dimensions soic-8 ep pd suffix case 751ac-01 issue a ?? ?? h c 0.10 d e1 a d pin one 2 x 8 x seating plane exposed gauge plane 14 5 8 d c 0.10 a-b 2 x e b e c 0.10 2 x top view side view bottom view detail a end view section a-a 8 x b a-b 0.25 d c c c 0.10 c 0.20 a a2 g f 1 4 58 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters (angles in degrees). 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. 4. datums a and b to be determined at datum plane h. dim min max millimeters a 1.35 1.75 a1 0.00 0.10 a2 1.35 1.65 b 0.31 0.51 b1 0.28 0.48 c 0.17 0.25 c1 0.17 0.23 d 4.90 bsc e 6.00 bsc e 1.27 bsc l 0.40 1.27 l1 1.04 ref f 2.24 3.20 g 1.55 2.51 h 0.25 0.50 0 8 h aa detail a (b) b1 c c1 0.25 l (l1) pad e1 3.90 bsc a1 location *for add itional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* exposed pad 1.52 0.060 2.03 0.08 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 7.0 0.275 2.72 0.107
ncv8508 http://onsemi.com 26 package dimensions d 2 pak-7 (short lead) dp suffix case 936ab-01 issue a dim min max min max millimeters inches a 0.396 0.406 10.05 10.31 b 0.326 0.336 8.28 8.53 c 0.170 0.180 4.31 4.57 d 0.026 0.036 0.66 0.91 e 0.045 0.055 1.14 1.40 g 0.050 ref 1.27 ref h 0.539 0.579 13.69 14.71 k l 0.000 0.010 0.00 0.25 m 0.100 0.110 2.54 2.79 n 0.017 0.023 0.43 0.58 notes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. a b k e p m n d g u v s h l c r 0.055 0.066 1.40 1.68 p 0.058 0.078 1.47 1.98 r s 0.095 0.105 2.41 2.67 u 0.256 ref 6.50 ref v 0.305 ref 7.75 ref 0 8 0 8 terminal 8 8.26 0.325 10.54 0.415 0.96 0.038 scale 3:1 mm inches 9.5 0.374 3.25 0.128 2.16 0.085 3.8 0.150 1.27 0.050 c l c l 1 *for a dditional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 ncv8508/d smart regulator is a registered trademark of semiconductor components industries, llc (scillc). literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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